Method of fabricating a semiconductor device and semiconductor device

ABSTRACT

A method of fabricating a semiconductor device and semiconductor device is provided. The method provides a first layer. The first layer includes through-holes. At least one semiconductor chip is provided. The semiconductor chip includes contact elements. The semiconductor chip is placed onto the first layer with the contact elements being aligned with the through-holes. An encapsulant material is applied over the semiconductor chip.

BACKGROUND

The present invention relates to a method of fabricating a semiconductordevice and a semiconductor device.

Semiconductor chips include contact pads of contact elements on one ormore of their surfaces. When fabricating a semiconductor device, in oneembodiment when housing the semiconductor chip in a semiconductor chippackage, the contact pads of the semiconductor chip have to be connectedto external contact elements of the semiconductor chip package.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of embodiments and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments andtogether with the description serve to explain principles ofembodiments. Other embodiments and many of the intended advantages ofembodiments will be readily appreciated as they become better understoodby reference to the following detailed description. The elements of thedrawings are not necessarily to scale relative to each other. Likereference numerals designate corresponding similar parts.

FIG. 1 illustrates a flow diagram of a method of fabricating asemiconductor device according to one embodiment.

FIGS. 2A-D illustrate schematic cross-sectional representations ofintermediate products and a semiconductor device for illustrating oneembodiment of a method of fabricating a semiconductor device.

FIG. 3 illustrates a flow diagram of a method of fabricating asemiconductor device according to one embodiment.

FIGS. 4A-D illustrate schematic cross-sectional representations ofintermediate products and a semiconductor device for illustrating oneembodiment of a method of fabricating a semiconductor device.

FIGS. 5A-M illustrate schematic cross-sectional representations ofintermediate products and a semiconductor device for illustrating oneembodiment of a method of fabricating a semiconductor device.

FIG. 6 illustrates a flow diagram of a method of fabricating a pluralityof semiconductor devices according to one embodiment.

FIGS. 7A-F illustrate schematic cross-sectional representations ofintermediate products and semiconductor devices for illustrating oneembodiment of a method of fabricating a plurality of semiconductordevices.

FIG. 8 illustrates a schematic cross-sectional representation of asemiconductor devices according to one embodiment.

FIG. 9 illustrates a schematic cross-sectional representation of asemiconductor device according to one embodiment.

FIG. 10 illustrates a schematic cross-sectional representation of asemiconductor device according to one embodiment.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments can be positioned in a number of differentorientations, the directional terminology is used for purposes ofillustration and is in no way limiting. It is to be understood thatother embodiments may be utilized and structural or logical changes maybe made without departing from the scope of the present invention. Thefollowing detailed description, therefore, is not to be taken in alimiting sense, and the scope of the present invention is defined by theappended claims.

It is to be understood that the features of the various exemplaryembodiments described herein may be combined with each other, unlessspecifically noted otherwise.

The aspects and embodiments are now described with reference to thedrawings, wherein like reference numerals are generally utilized torefer to like elements throughout. In the following description, forpurposes of explanation, numerous specific details are set forth inorder to provide a thorough understanding of one or more aspects of theembodiments. It may be evident, however, to one skilled in the art thatone or more aspects of the embodiments may be practiced with a lesserdegree of the specific details. In other embodiments, known structuresand elements are illustrated in schematic form in order to facilitatedescribing one or more aspects of the embodiments. It is to beunderstood that other embodiments may be utilized and structural orlogical changes may be made without departing from the scope of thepresent invention. It should be noted further that the drawings are notto scale or not necessarily to scale.

In addition, while a particular feature or aspect of one embodiment maybe disclosed with respect to only one of several implementations, suchfeature or aspect may be combined with one or more other features oraspects of the other implementations as may be desired and advantageousfor any given or particular application. Furthermore, to the extent thatthe terms “include”, “have”, “with” or other variants thereof are usedin either the detailed description or the claims, such terms areintended to be inclusive in a manner similar to the term “comprise”. Theterms “coupled” and “connected”, along with derivatives may be used. Itshould be understood that these terms may be used to indicate that twoelements co-operate or interact with each other regardless whether theyare in direct physical or electrical contact, or they are not in directcontact with each other. Also, the term “exemplary” is merely meant asan example, rather than the best or optimal. The following detaileddescription, therefore, is not to be taken in a limiting sense, and thescope of the present invention is defined by the appended claims.

The embodiments of a method of fabricating a semiconductor device andthe embodiments of a semiconductor device may use various types ofsemiconductor chips or semiconductor substrates, among them logicintegrated circuits, analog integrated circuits, mixed signal integratedcircuits, sensor circuits, MEMS (Micro-Electro-Mechanical Systems),power integrated circuits, chips with integrated passives, discretepassives and so on. In general the term “semiconductor chip” as used inthis application can have different meanings one of which is asemiconductor die or semiconductor substrate including an electricalcircuit.

In several embodiments layers or layer stacks are applied to one anotheror materials are applied or deposited onto layers. It should beappreciated that any such terms as “applied” or “deposited” are meant tocover literally all kinds and techniques of applying layer onto eachother. In one embodiment, they are meant to cover techniques in whichlayers are applied at once as a whole, like, for example, laminatingtechniques, as well as techniques in which layers are deposited in asequential manner, like, for example, sputtering, plating, molding,chemical vapor deposition (CVD) and so on.

The semiconductor chips may include contact elements or contact pads onone or more of their outer surfaces wherein the contact elements servefor electrically contacting the semiconductor chips. The contactelements may be made from any electrically conducting material, e.g.,from a metal as aluminum, gold, or copper, for example, or a metalalloy, or an electrically conducting organic material, or anelectrically conducting semiconductor material.

The semiconductor chips may become covered with an encapsulatingmaterial. The encapsulating material can be any electrically insulatingmaterial like, for example, any kind of molding material, any kind ofepoxy material, or any kind of resin material. In special cases it couldbe advantageous to use a conductive encapsulant material. In the processof covering the semiconductor chips or dies with the encapsulatingmaterial, fan-out embedded dies can be fabricated. The fan-out embeddeddies can be arranged in an array having the form e.g., of a wafer andwill thus be called a “re-configured wafer” further below. However, itshould be appreciated that the fan-out embedded die array is not limitedto the form and shape of a wafer but can have any size and shape and anysuitable array of semiconductor chips embedded therein.

Referring to FIG. 1, there is illustrated a flow diagram of a method offabricating a semiconductor device according to one embodiment. Themethod includes providing a first layer, the first layer includingthrough-holes (s1), providing at least one semiconductor chip, thesemiconductor chip defining a first surface including contact elementsand a second surface opposite to the first surface of the semiconductorchip (s2), placing the semiconductor chip onto the first layer with thefirst surface facing the first layer (s3), and applying an encapsulantmaterial over the second surface of the semiconductor chip (s4).

According to one embodiment of the method of fabricating a semiconductordevice, the method further includes placing the semiconductor chip ontothe first layer with the contact elements being aligned with thethrough-holes.

According to one embodiment of the method of fabricating a semiconductordevice, the through-holes are formed by at least one of stamping, laserdrilling, or selectively etching the first layer.

According to one embodiment of the method of fabricating a semiconductordevice, the first layer is an insulation layer.

According to one embodiment of the method of fabricating a semiconductordevice, the first layer is comprised of a first insulation layer facingthe semiconductor chip and a metal layer facing away from thesemiconductor chip. The metal layer may include the function of a seedlayer for a later metallization process.

According to one embodiment of the method of fabricating a semiconductordevice, the first layer is attached to a second layer. According to afurther embodiment thereof, the second layer is separated from the firstlayer after placing the semiconductor chip onto the first layer and theencapsulation.

According to one embodiment of the method of fabricating a semiconductordevice, the method further includes applying a conducting layer over thefirst layer and the contact elements wherein the conducting layer mayinclude conducting areas which are aligned with the through-holes andwhich can be electrically connected with the contact elements of thesemiconductor chips by filling electrically conductive material into thethrough-holes. The conducting layer may include the function of aredistribution layer for redistributing the arrangement of the contactelements over a larger area.

According to one embodiment of the method of fabricating a semiconductordevice, the method further includes applying solder balls andelectrically connecting the solder balls with the contact elements ofthe semiconductor chip. According to one embodiment thereof, the methodfurther includes applying a solder resist layer, the solder resist layerincluding openings wherein the solder balls are applied above theopenings of the solder resist layer.

Referring to FIGS. 2A-D, there are illustrated cross-sectionalrepresentations of intermediate products and a semiconductor device forillustrating one embodiment of a method of fabricating a semiconductordevice corresponding to the embodiment of FIG. 1. FIG. 2A illustrates across-sectional representation of a first layer 1 wherein the firstlayer 1 includes through-holes 1A. The first layer 1 can be made of adielectric, insulating material which can, for example, be comprised ofa foil based on an acrylate or which can also be an epoxy-bistage foil.The first layer 1 can, for example, also be made of a prepreg(preimpregnated) foil such as that known from conventional substratetechnology. The first layer 1, for example, can be comprised of aphoto-structurable prepreg which can be etched after lithographicalexposure. It is also possible that the first layer 1 could be ablated orstructured with a laser beam. The first layer 1 can also include anadditive, which releases electrically conducting material or whichreleases a catalytic layer for plating upon irradiation. The first layer1 can also have adhesion properties in order to fix semiconductor chipswhich are to be applied on its surface. If, however, the first layer 1does not have itself sufficient adhesion force at its surface, a thirdlayer (not illustrated) including an adhesion promoter can be applied tothe surface of the first layer 1.

The through-holes 1A can be produced, for example, by one of stamping,laser drilling, or selective etching of the first layer 1.

FIG. 2B illustrates a cross-sectional representation of a semiconductorchip 2 including a first surface having contact elements or contact pads2A thereon, and a second surface opposite to the first surface. Thesemiconductor chips to be used here may be of extremely different typesand may include integrated electrical or electro-optical circuits. Thesemiconductor chips may be, for example, configured as powertransistors, power diodes, control circuits, micro-processors ormicro-electro-mechanical components or discrete passives. Thesemiconductor chips need not necessarily be manufactured from specificsemiconductor material and, furthermore, may contain inorganic and/ororganic materials that are not semiconductors, such as, for example,insulators, plastics or metals.

FIG. 2C illustrates an intermediate product after applying thesemiconductor chip 2 to the first layer 1. The semiconductor chip 2 isplaced onto the first layer 1 with the first surface of thesemiconductor chip 2 facing the first layer 1. The semiconductor chip 2can be placed in such a way onto the first layer 1 that the contactelements 2A of the semiconductor chip 2 are aligned with thethrough-holes 1A of the first layer 1. The semiconductor chip 2 can beplaced by different means onto the first layer 1 wherein, for example,in case of placing a plurality of semiconductor chips 2 onto the firstlayer 1, a pick-and-place machine can be used. A pattern recognition ofthe through-holes can be implemented for placing the semiconductor chipin the correct position.

FIG. 2D illustrates a cross-sectional representation of a semiconductordevice after applying an encapsulant material 3 over the semiconductorchip 2. The encapsulant material 3 can, for example, include a moldingmaterial wherein the molding technique can be, for example, compressionmolding. The encapsulant material can also be applied by other processtechniques like, for example, screen printing. The encapsulant materialsinclude, for example, aliphatic and aromatic polymers includingthermoplastic and thermoset type polymers and blends of these and alsoother various types of polymers.

Typical values of the thicknesses of the layers may be as follows. Thethickness of the first layer 1 typically ranges from 5 μm to 150 μm,whereas the thickness of the semiconductor chip 2 typically ranges from50 μm to 450 μm, and the thickness of the encapsulant material typicallyranges from 300 μm to 700 μm.

Referring to FIG. 3, there is illustrated a flow diagram of a method offabricating a semiconductor device according to one embodiment. Themethod includes providing a first layer, the first layer includingthrough-holes (s1), providing at least one semiconductor chip, thesemiconductor chip including contact elements (s2), placing thesemiconductor chip onto the first layer with the contact elements beingaligned with the through-holes (s3), and applying an encapsulantmaterial over the semiconductor chip.

According to one embodiment of the method of fabricating a semiconductordevice, the method further includes the semiconductor chip defining afirst surface including the contact elements and a second surfaceopposite to the first surface, and placing the semiconductor chip ontothe first layer with the first surface facing the first layer.

There can be provided further embodiments of the method of fabricating asemiconductor device corresponding with the embodiment as describedabove in connection with the semiconductor device as depicted in FIGS. 1and 2.

Referring to FIGS. 4A-D, there are illustrated cross-sectionalrepresentations of intermediate products and a semiconductor device forillustrating one embodiment of a method of fabricating a semiconductordevice corresponding to the embodiment of FIG. 3. FIG. 4A illustrates across-sectional representation of a first layer 1 wherein the firstlayer 1 includes through-holes 1A. The first layer 1 can be made of adielectric, insulating material which can, for example, be comprised ofa foil based on an acrylate or which can also be an epoxy-B-stage foil.The first layer 1 can, for example, also be made of a prepreg(preimpregnated) foil such as that known from conventional substratetechnology. The first layer 1, for example, can be comprised of a photostructurable prepreg which can be etched after lithographical exposure.It is also possible that the first layer 1 could be ablated orstructured with a laser beam. The first layer 1 can also include anadditive, which releases electrically conducting material or whichreleases a catalytic layer for plating upon irradiation. The first layer1 can also have adhesion properties in order to fix semiconductor chipswhich are to be applied on its surface. If, however, the first layerdoes not have itself sufficient adhesion force at its surface, a thirdlayer (not illustrated) including an adhesion promoter can be applied tothe surface of the first layer 1.

The through-holes 1A can be produced, for example, by stamping, laserdrilling, or etching of the first layer 1.

FIG. 4B illustrates a cross-sectional representation of a semiconductorchip including a first surface having contact elements or contact pads2A thereon, and a second surface opposite to the first surface. Thesemiconductor chips to be used here may be of extremely different typesand may include for integrated electrical or electro-optical circuits.The semiconductor chips may be, for example, configured as powertransistors, power diodes, control circuits, micro-processors ormicro-electro-mechanical components. The semiconductor chips need not bemanufactured from specific semiconductor material and, furthermore, maycontain inorganic and/or organic materials that are not semiconductors,such as, for example, insulators, plastics or metals.

FIG. 4C illustrates an intermediate product after applying thesemiconductor chip 2 to the first layer 1. The semiconductor chip 2 isplaced onto the first layer 1 with the first surface of thesemiconductor chip 2 facing the first layer 1. The semiconductor chip 2can be placed in such a way onto the first layer 1 that the contactelements 2A of the semiconductor chip 2 are aligned with thethrough-holes 1A of the first layer 1. The semiconductor chip 2 can beplaced by different means onto the first layer 1 wherein, for example,in case of placing a plurality of semiconductor chips 2 onto the firstlayer 1, a pick-and-place machine can be used.

FIG. 4D illustrates a cross-sectional representation of a semiconductordevice after applying an encapsulant material 3 over the semiconductorchip 2. The encapsulant material 3 can, for example, include a moldingmaterial wherein the molding technique can be, for example, compressionmolding. The encapsulant material can also be applied by other processtechniques like, for example, screen printing. The encapsulant materialsinclude, for example, aliphatic and aromatic polymers includingthermoplastic and thermoset type polymers and blends of these and alsoother various types of polymers.

Typical values of the thicknesses of the layers may be as follows. Thethickness of the first layer 1 typically ranges from 5 μm to 150 μm,whereas the thickness of the semiconductor chip 2 typically ranges from150 μm to 450 μm, and the thickness of the encapsulant materialtypically ranges from 300 μm to 700 μm.

According to one embodiment of the embodiments as described in thisapplication, the through-holes are formed into the first layer in astage of the process in which the at least one semiconductor chip hasnot yet been applied to the first layer. Therefore, there are nospecific restrictions in handling of the first layer and no particularmeasures to be taken in order to prevent any damages. The through-holescan therefore be easily formed by any sort of process like, for example,stamping of the first layer, laser drilling or laser structuring of thefirst layer, selective etching of the first layer and so on.Furthermore, a metallic layer can be grown on or deposited on the firstlayer which metallic layer is to be utilized for later electro platingor galvanic processes. The metallic layer can also be deposited onto thefirst layer without any particular restrictions or measures to be taken.A further advantage lies in the fact that the semiconductor chips can beapplied to the first layer and they can be easily placed onto the firstlayer with the contact elements of the semiconductor chips being alignedwith the through-holes of the first layer. The through-holes can beutilized for a pattern recognition of an automated process of placing ofthe semiconductor chips by using, for example, a pick-and-place-machine.

Referring to FIGS. 5A-M, there are illustrated cross-sectionalrepresentations of intermediate products and semiconductor devices forillustrating a method of fabricating a semiconductor device according toone embodiment. FIG. 5A illustrates a layer stack including a firstlayer 1 which may correspond to the first layer 1 as described in theprevious embodiments, i.e. which may be fabricated of a dielectricresin. On one surface of the first layer 1 a thin metallic layer 4 isdeposited. The metallic layer 4 serves the purpose of a seed layerutilized to assist a metallization plating process, e.g., a galvanicmetallization process, which is performed in a later process for thefabrication of a redistribution layer. The metallic layer 4 can have athickness in a range from 20 nm to 300 nm. It can be deposited as asingle layer of, for example, an element metal like Ti or Cu or it canbe deposited as a layer stack including, for example, a 50 nm Ti layerand a Cu layer of a thickness between 100 nm and 200 nm. The metalliclayer 4 can be produced by different ways. It, for example, can beproduced by depositing onto the surface of the first layer 1, in oneembodiment by sputtering. It is also possible to choose a specificmaterial of the first layer 1, the specific material containing anadditive, which releases electrically conducting material uponirradiation. The specific material may also release upon irradiation acatalytic starter for a subsequent plating process. It is also possibleto omit the metallic layer 4 which will be explained further below. Thelayer stack as illustrated in FIG. 5A also illustrates an auxiliarylayer 5 which is applied onto the first layer 1 or the metallic layer 4.The auxiliary layer 5 may include the form of a transparent tape and itmay serve the purpose of a protection tape which is to be removed in alater stage.

FIG. 5B illustrates a cross sectional representation of a furtherintermediate product. The intermediate product of FIG. 5B is obtainedafter producing through-holes 1A into the first layer 1. Thethrough-holes 1A can be produced by photo-structuring of the first layer1 by using a laser beam if the first layer 1 is made of aphoto-structurable material. If the material of the first layer 1 is notonly comprised of a photo-structurable material but also contains anadditive, which releases electrically conducting material as describedabove, it would be possible to generate the through-holes 1A and at thesame time to generate a thin electrically conducting surface layer atthe walls of the through-holes 1A. The structuring of the first layer 1by laser irradiation can be performed e.g., by a scanned laser beam orby an optical imaging system including a conventional (incoherent) lightsource, a mask and a lens. The structuring of the first layer 1 can alsobe performed by a stamping process or by a selective etching process ofthe first layer 1.

FIG. 5C illustrates a cross-sectional representation of a furtherintermediate product obtained after applying of a semiconductor chip 2to the first layer 1. The semiconductor chip 2 will be placed onto asurface of the first layer 1 which is situated opposite to the(optional) metallic layer 4 and the (optional) auxiliary layer 5. Thesemiconductor chip 2 includes contact elements 3A and will be placedsuch that the contact elements 3A are aligned with the through-holes 1Aof the first layer 1. The semiconductor chip 2 can be placed by use of apick-and-place-machine which can be equipped with a pattern recognitiontool using the through-holes 1A as an orientation for the placementprocess. In the embodiment of FIGS. 5A-M only two contact elements 2Aper chip 2 are illustrated. However, it should be noted that the chip 2can have even more contact elements.

FIG. 5D illustrates a cross-sectional representation of a furtherintermediate product obtained after applying an encapsulant material 3onto the semiconductor chip 2. The encapsulant material can be made ofany material as described in one of the previous embodiments. Theencapsulant material can be applied in such a way onto the semiconductorchip 2 so that the semiconductor chip 2 is embedded in the encapsulantmaterial, in one embodiment surrounded by the encapsulant material onall sides besides the surface on which the contact elements 2A areprovided. After applying of the encapsulant material, a tempering orcuring process is performed for curing or hardening the encapsulantmaterial.

FIG. 5E illustrates a cross-sectional representation of a furtherintermediate product obtained after removing the auxiliary layer 5 andfilling a conductive ink 6 into the through-holes 1A. The intermediateproduct is illustrated upside down with respect to the previous drawingof FIG. 5D. The conductive ink 6 can be comprised of, for example, anyliquid medium in which electrically conductive particles, in oneembodiment microscopic particles like nano-particles are embeddedwherein e.g., silver nano-particles could be used. The through-holes 1Acould be filled each with an amount of 3 to 40 pl per drop of conductiveink 6. The application of the conductive ink 6 and the subsequent dryingand/or curing provides a conducting seed layer on the bottom of thethrough-holes 1A, i.e. on the contact elements 2A of the semiconductorchip 2 and the side walls of the through-holes 1A. The ink-jetting canalso be performed with the help of pattern recognition on the basis ofthe location of the through-holes 1A. The curing of the deposited inkcould be performed in a way that the encapsulant material 3 will becured or post-cured at the same time. The curing temperature should behigher than 150° C., in one embodiment higher than 200° C. in order toensure a good conductivity of the cured conductive ink 6. After curingof the conductive ink 6 the walls of the through-holes 1A and thecontact elements 2A are covered with a conductive material, theconductive material being comprised of conductive particles embedded ina matrix.

In one embodiment, no metallic layer 4 is applied to the first layer 1when fabricating the intermediate product of FIG. 5A; so whenfabricating the intermediate product of FIG. 5E, the conductive ink 6 isapplied to the whole upper surface of the first layer 1 including thethrough-holes 1A.

In FIG. 5F there is illustrated a cross-sectional representation of afurther intermediate product after application of a resist layer 7 ontothe upper surface of the metallic layer 4 and the through-holes 1A ofthe first layer 1. The resist layer 7 can be comprised of a dry resistor a sprayed resist which may have a thickness of, for example, 10 μm-30μm, in one embodiment 15 μm. The resist layer 7 can be laminated ontothe surface of the metallic layer 4 if it is in the form of a dryresist.

FIG. 5G illustrates a cross-sectional representation of a furtherintermediate product after exposing and developing the resist layer 7.The resist layer 7, for example, can be exposed with a laser directimaging (LDI) process or with any other conventional imaging method.After developing of the resist layer 7, predetermined portion of theresist layer are removed in order to fabricate electrically conductivecontact areas thereon.

FIG. 5H illustrates a cross-sectional representation of a furtherintermediate product after forming contact areas 8A into thethrough-holes 1A and on the regions of the metallic layer 4 which areconnected with the through-holes 1A, respectively. The contact areas 8Aare intended to form part of a redistribution layer 8 for redistributingthe distribution of the contact elements 2A to a larger area. Thecontact areas 8A can, for example, be fabricated by electro-plating in astrong agitated electrolyte. In FIG. 5H there is illustrated only onecontact area 8A to its full extent, the contact area 8A being connectedwith the right one of the through-holes 1A as illustrated. It is to beunderstood that the other contact areas 8A may also be fabricated withthe same geometric dimensions, wherein, for example, the contact area 8Aconnected with the left through-hole 1A may extend in a directionperpendicular to the image plane. The contact areas 8A can be producedby galvanic plating or by other means like, for example, chemicalplating or even by a screen printing process.

FIG. 5I illustrates a cross-sectional representation of a furtherintermediate product after etching of the remaining portions of theresist layer 7.

FIG. 5J illustrates a cross-sectional representation of a furtherintermediate product obtained after etching of the remaining portions ofthe metallic layer 4 under the remaining portions of the resist layer 7removed in the process before so that the contact areas 8A of theredistribution layer 8 become electrically separated from each other. Incase of the above-mentioned alternative embodiment in which no metalliclayer is deposited onto the first layer 1 from the beginning but insteada conductive ink layer is applied onto the entire surface of the firstlayer 1 to obtain the intermediate product of FIG. 5E, the remainingportions of the conductive ink layer are removed between the contactareas 8A. In the case of screen printing no seed layer will have to beapplied.

FIG. 5K illustrates a cross sectional representation of a furtherintermediate product obtained after applying and structuring of a solderresist layer 9. The solder resist layer 9 is structured so thatessential or large portions of the contact areas 8A are not covered bythe solder resist layer 9.

In FIG. 5L there is illustrated a cross-sectional representation of afurther intermediate product obtained after filling solder balls 10 intothe openings of the solder resist layer 9 so that each solder ball 10 isconnected with one of the contact areas 8A of the redistribution layer8, respectively.

In FIG. 5M there is illustrated a cross-sectional representation of afurther intermediate product obtained after applying further material ofthe solder resist in regions at the bottom of the solder balls 10 inorder to stabilize and strengthen the fixation of the solder balls 10within the openings of the solder resist layer 9.

Referring to FIG. 6, there is illustrated a flow diagram of a method offabricating a plurality of semiconductor devices according to oneembodiment. The method includes providing a first layer, the first layerincluding through-holes (s1), providing a plurality of semiconductorchips, each one of the semiconductor chips defining a first surfaceincluding contact elements and a second surface opposite to the firstsurface of the semiconductor chips and side surfaces between the firstand second surfaces, respectively (s2), placing the semiconductor chipsonto the first layer with the first surface facing the first layer (s3),applying an encapsulant material over at least the side surfaces of thesemiconductor chips (s4), applying a conducting layer over the firstlayer and the contact elements, the conducting layer includingconducting areas, each one of the conducting areas connected with one ofthe contact elements, respectively (s5), and dividing the resultingstructure into semiconductor devices (s6).

According to one embodiment of the method of fabricating a plurality ofsemiconductor devices, the method further includes placing thesemiconductor chips onto the first layer with the contact elements beingaligned with the through-holes.

According to one embodiment of the method of fabricating a plurality ofsemiconductor devices, the through-holes are formed by at least one ofstamping, laser drilling, or selective etching the first layer.

According to one embodiment of the method of fabricating a plurality ofsemiconductor devices, the first layer is an insulating layer.

According to one embodiment of the method of fabricating a plurality ofsemiconductor devices, the first layer is comprised of a firstinsulation layer facing the semiconductor chips and a metal layer facingaway from the semiconductor chips.

According to one embodiment of the method of fabricating a plurality ofsemiconductor devices, the first layer is attached to a second layer.According to a further embodiment thereof, the second layer is separatedfrom the first layer after placing the semiconductor chips onto thefirst layer and encapsulating the semiconductor chips.

Referring to FIGS. 7A-E, there are illustrated cross-sectionalrepresentations of intermediate products and semiconductor devices forillustrating a method of fabricating a plurality of semiconductordevices according to one embodiment of the embodiment as depicted inFIG. 6. This embodiment illustrates a complete embedding packagingprocess. FIG. 7A illustrates a cross-sectional representation of a firstlayer 1, the first layer 1 including through-holes 1A, and of aplurality of semiconductor chips 2, wherein each one of thesemiconductor chips 2 defines a first surface including contact elements2A and a second surface opposite to the first surface of thesemiconductor chips 2, respectively.

FIG. 7B illustrates a cross-sectional representation of an intermediateproduct obtained after placing the plurality of semiconductor chips 2onto the first layer 1 with the first surface of the semiconductor chips2 facing the first layer 1. The semiconductor chips 2 are placed ontothe first layer 1 with a sufficient spacing from each other in order toallow a fan-out of the electrical contacts. A pick-and-place-machine canbe used for placing the semiconductor chips 2 onto the first layer 1.There are illustrated three semiconductor chips 2 which is to beunderstood only as an example. In fact the number of semiconductor chipscan be much higher than that and the semiconductor chips 2 can be placedin the form of a regular array onto the first layer 1. Also thesemiconductor chip 2 can represent a multichip arrangement resulting ina system-in-package (SIP).

In FIG. 7C there is illustrated a cross-sectional representation of afurther intermediate product obtained after applying an encapsulantmaterial 3 onto the semiconductor chips 2 so that the semiconductorchips 2 are embedded in the encapsulant material 3. The encapsulantmaterial can be applied by, for example, molding, in one embodiment byusing a mold form corresponding to the form of a wafer so that anembedded wafer can be formed.

FIG. 7D illustrates a cross-sectional representation of a furtherintermediate product obtained after applying a conducting layer 8 overthe first layer 1 and the contact elements 2A, the conducting layer 8including conducting areas 8A, each one of the conducting areas 8Aconnected with one of the contact elements 2A of the semiconductor chips2, respectively.

FIG. 7E illustrates a cross-sectional representation of an intermediateproduct obtained after applying a solder resist layer 9. The solderresist layer 9 is structured after being applied so that it formsopenings 9A, the openings 9A of the solder resist layer 9 being alignedwith the contact areas 8A of the conducting layer 8. According to afurther embodiment the solder resist is applied in a structured form by,for example, a printing process like e.g., ink jetting or screen orstencil printing.

FIG. 7F illustrates a cross-sectional representation of an intermediateproduct obtained after filling solder balls 10 into the openings 9A ofthe solder resist layer 9. The solder balls 10 are thus electricallyconnected to the contact areas 8A and extend outwardly over the surfaceof the solder resist layer 9. Finally, as illustrated by the dashedlines, the resulting structure is divided along the dashed lines toreveal a plurality of semiconductor devices.

In FIG. 8 there is illustrated a cross-sectional representation of asemiconductor device or a semiconductor chip package according to oneembodiment. The semiconductor chip package 20 includes at least onesemiconductor chip 2 including contact elements 2A on a first surface ofthe semiconductor chip 2, an encapsulant material 3 covering at leastpartly the semiconductor chip 2, a dielectric layer 1 situated on thefirst surface of the semiconductor chip 2, the dielectric layer 1including through-holes 1A aligned with the contact elements 2A, and alayer 26 of a conductive material covering a surface of the dielectriclayer 1 above the through-holes 1A, the conductive material beingproduced by applying conductive ink to the surface and one or more ofdrying, curing and sintering the conductive ink.

According to one embodiment of the semiconductor device 20, thesemiconductor device 20 further includes a conducting layer includingconducting areas, each one of the conducting areas connected withrespective contact elements 2A by an electrically conducting materialfilled in the through-holes 1A, respectively, wherein the conductingmaterial can be conductive ink. According to a further embodimentthereof, the semiconductor device 20 further includes a solder resistlayer applied above the conducting layer, the solder resist layerincluding openings above the conducting areas. According to a furtherembodiment thereof, the semiconductor device 20 further includes solderballs applied above the openings of the solder resist layer, the solderballs being electrically connected to the contact areas, respectively.

Referring to FIG. 9, there is illustrated a cross-sectionalrepresentation of a semiconductor device according to one embodiment.The semiconductor device 30 as illustrated in FIG. 9 includes at leastone semiconductor chip 2 including contact elements 2A on a firstsurface of the semiconductor chip 2, an encapsulant material 3 coveringat least partly the semiconductor chip 2, a dielectric layer 1 situatedon the first surface of the semiconductor chip 2, the dielectric layer 1including through-holes 1A aligned with the contact elements 2A, and alayer 36 of a conductive material covering a surface of the dielectriclayer 1 above the through-holes 1A, the conductive material beingcomprised of conductive particles embedded in a matrix.

According to one embodiment of the semiconductor device 30, thesemiconductor device 30 further includes a conducting layer includingconducting areas, each one of the conducting areas connected withrespective contact elements 2A by an electrically conducting materialfilled in the through-holes 1A, respectively, wherein the conductingmaterial can be conductive ink or conductive paste. According to afurther embodiment thereof, the semiconductor device 30, furtherincludes a solder resist layer applied above the conducting layer, thesolder resist layer including openings above the contact areas.According to a further embodiment thereof, the semiconductor device 30further includes solder balls applied above the openings of the solderresist layer, the solder balls being electrically connected to thecontact areas, respectively.

In FIG. 10 there is illustrated a cross-sectional representation of asemiconductor device or a semiconductor chip package according to oneembodiment. The semiconductor chip package 40 includes at least onesemiconductor chip 2 including contact elements 2A on a first surface ofthe semiconductor chip 2, an encapsulant material 3 covering at leastpartly the semiconductor chip 2, a dielectric layer 1 situated on thefirst surface of the semiconductor chip 2, the dielectric layer 1including through-holes 1A aligned with the contact elements 2A, and alayer 46 of a conductive material covering a surface of the dielectriclayer 1 above the through-holes 1A, the layer 46 being produced by asputtering process. According to one embodiment the layer 46 is asputtered metallic layer including an element metal or metal alloy.

According to one embodiment of the semiconductor device 40, thesemiconductor device 40 further includes a conducting layer includingconducting areas, each one of the conducting areas connected withrespective contact elements 2A by an electrically conducting materialfilled in the through-holes 1A, respectively, wherein the conductingmaterial can be conductive ink. According to a further embodimentthereof, the semiconductor device 20 further includes a solder resistlayer applied above the conducting layer, the solder resist layerincluding openings above the conducting areas. According to a furtherembodiment thereof, the semiconductor device 20 further includes solderballs applied above the openings of the solder resist layer, the solderballs being electrically connected to the contact areas, respectively.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

1. A method of fabricating a semiconductor device, comprising: providinga first layer, the first layer comprising through-holes; providing atleast one semiconductor chip, the semiconductor chip defining a firstsurface comprising contact elements and a second surface opposite to thefirst surface of the semiconductor chip; placing the semiconductor chiponto the first layer with the first surface facing the first layer; andapplying an encapsulant material over the second surface of thesemiconductor chip.
 2. The method of claim 1, further comprising:placing the semiconductor chip onto the first layer with the contactelements being aligned with the through-holes.
 3. The method of claim 1,further comprising forming the through-holes by at least one ofstamping, laser drilling, and selective etching the first layer.
 4. Themethod of claim 1, wherein the first layer is an insulating layer. 5.The method of claim 1, wherein the first layer is comprised of a firstinsulation layer facing the semiconductor chip and a metal layer facingaway from the semiconductor chip.
 6. The method of claim 1, furthercomprising attaching the first layer to a second layer.
 7. The method ofclaim 6, further comprising separating the second layer from the firstlayer after placing the semiconductor chip onto the first layer.
 8. Themethod of claim 1, further comprising fabricating an encapsulatedstructure having a shape of a wafer.
 9. The method of claim 1, furthercomprising fabricating an encapsulated structure having a rectangularshape.
 10. A method of fabricating a semiconductor device, comprising:providing a first layer, the first layer comprising through-holes;providing at least one semiconductor chip, the semiconductor chipcomprising contact elements; placing the semiconductor chip onto thefirst layer with the contact elements being aligned with thethrough-holes; and applying an encapsulant material over thesemiconductor chip.
 11. The method of claim 10, further comprising thesemiconductor chip defining a first surface comprising the contactelements and a second surface opposite to the first surface, and placingthe semiconductor chip onto the first layer with the first surfacefacing the first layer.
 12. The method of claim 10, further comprisingforming the through-holes by at least one of stamping, laser drilling,or selective etching the first layer.
 13. The method of claim 10,wherein the first layer is an insulating layer.
 14. The method of claim10, wherein the first layer is comprised of a first insulation layerfacing the semiconductor chip and a metal layer facing away from thesemiconductor chip.
 15. The method of claim 10, further comprisingattaching the first layer to a second layer.
 16. The method of claim 15,further comprising separating the second layer from the first layerafter placing the semiconductor chip onto the first layer.
 17. Themethod of claim 10, further comprising fabricating an encapsulatedstructure having a shape of a wafer.
 18. The method of claim 10, furthercomprising fabricating an encapsulated structure having a rectangularshape.
 19. A method of fabricating a plurality of semiconductor devices,comprising: providing a first layer, the first layer comprisingthrough-holes; providing a plurality of semiconductor chips, each one ofthe semiconductor chips defining a first surface comprising contactelements and a second surface opposite to the first surface of thesemiconductor chips and side surfaces between the first and secondsurfaces, respectively; placing the semiconductor chips onto the firstlayer with the first surface facing the first layer; applying anencapsulant material over at least the side surfaces of thesemiconductor chips; applying a conducting layer over the first layerand the contact elements, the conducting layer comprising conductingareas, each one of the conducting areas connected with one of thecontact elements, respectively; and dividing the resulting structureinto semiconductor devices.
 20. The method of claim 19, furthercomprising placing the semiconductor chips onto the first layer with thecontact elements being aligned with the through-holes.
 21. The method ofclaim 19, further comprising forming the through-holes by at least oneof stamping, laser drilling, or selective etching the first layer. 22.The method of claim 19, wherein the first layer is an insulating layer.23. The method of claim 19, wherein the first layer is comprised of afirst insulation layer facing the semiconductor chips and a metal layerfacing away from the semiconductor chips.
 24. The method of claim 19,further comprising attaching the first layer to a second layer.
 25. Themethod of claim 24, further comprising separating the second layer fromthe first layer after placing the semiconductor chips onto the firstlayer.
 26. The method of claim 19, further comprising fabricating anencapsulated structure having a shape of a wafer.
 27. The method ofclaim 19, further comprising fabricating an encapsulated structurehaving a rectangular shape.
 28. A semiconductor device, comprising: atleast one semiconductor chip comprising contact elements on a firstsurface of the chip; a encapsulant material covering at least partly thesemiconductor chip; a dielectric layer situated on the first surface ofthe chip, a dielectric layer situated on the first surface of the chip,the dielectric layer comprising vias aligned with the contact elements;and a layer of a conductive material covering a surface of thedielectric layer above the vias, the conductive material produced byapplying conductive ink to the surface and one or more of drying, curingand sintering the conductive ink.
 29. The semiconductor device of claim28, further comprising: a conducting layer comprising contact areas,each one of the contact areas connected with the vias, respectively. 30.The semiconductor device of claim 29, further comprising: a solderresist layer applied above the conducting layer, the solder resist layercomprising openings above the contact areas.
 31. The semiconductordevice of claim 30, further comprising: solder balls applied above theopenings of the solder resist layer, the solder balls being electricallyconnected to the contact areas, respectively.
 32. A semiconductordevice, comprising: at least one semiconductor chip comprising contactelements on a first surface of the semiconductor chip; an encapsulantmaterial covering at least partly the semiconductor chip; a dielectriclayer situated on the first surface of the semiconductor chip, thedielectric layer comprising vias aligned with the contact elements; anda layer of a conductive material covering a surface of the dielectriclayer above the vias, the conductive material being comprised ofconductive particles embedded in a matrix.
 33. The semiconductor deviceof claim 32, further comprising: a conducting layer comprising contactareas, each one of the contact areas connected with one of the vias,respectively.
 34. The semiconductor device of claim 33, furthercomprising: a solder resist layer applied above the conducting layer,the solder resist layer comprising openings above the contact areas. 35.The semiconductor device of claim 34, further comprising: solder ballsapplied above the openings of the solder resist layer, the solder ballsbeing electrically connected to the contact areas, respectively.